1. Field of the Invention
The present invention relates to integrated circuit packaging, and more particularly, to improved routing in integrated circuit packages and in circuit boards to which they are mounted.
2. Background Art
Integrated circuit (IC) dies are typically mounted in or on a package that is attached to a printed circuit board (PCB). One such type of IC die package is a ball grid array (BGA) package. BGA packages provide for smaller footprints than many other package solutions available today. A BGA package has an array of solder ball pads located on a bottom external surface of a package substrate. Solder balls are attached to the solder ball pads. The solder balls are reflowed to attach the package to the PCB. The IC die is mounted to a top surface of the package substrate. Wire bonds typically couple signals of the IC die to the substrate. The substrate has internal routing which electrically couples the IC die signals to the solder balls on the bottom substrate surface.
BGA packages are widely used in the IC packaging industry. BGA packages have many beneficial characteristics, including high reliability, a relatively mature assembly process, relatively low cost, and good thermal and electrical performances. Existing BGA packages, however, have limitations that affect their ability to be used for advanced IC die applications.
Increasingly more functions are being integrated into individual IC dies. Thus, BGA package substrates must interface a greater number of input/output (I/O) signals, and powers and grounds, with the PCB. Thus, signal routing in both the package substrate and PCB is becoming more complex. Hence, to accommodate these difficulties, increasingly larger BGA package sizes are being used, with larger arrays of solder ball pads. Furthermore, the number of layers of the package substrate is increasing. However, these changes have undesirable consequences, including an increase in the cost of the BGA package, and a larger BGA package footprint on the PCB.
Hence, what is needed are BGA packages that can accommodate increasingly larger IC dies, while maintaining or reducing the overall BGA package size. Furthermore, what is needed are techniques for reducing the complexity of BGA package and related PCB signal routing.